Synopsys and TSMC Expand AI Chip Design Collaboration

The collaboration centers on the certification of EDA flows for TSMC’s A14 process, providing a unified path from initial design to final signoff. By leveraging agentic AI, the companies are automating labor-intensive tasks in analog, digital, and multi-die floorplanning. Tools such as Fusion Compiler now utilize LLM-assisted analysis to boost engineering productivity, while 3DIC Compiler streamlines the integration of complex chiplet architectures.

Addressing the thermal and power demands of modern AI systems, the partnership also targets advanced packaging technologies like CoWoS and TSMC-COUPE. These efforts enable co-design of integrated voltage regulators and co-packaged optics, critical for high-speed connectivity. Furthermore, the companies have reached significant milestones in silicon-proven IP, including successful tape-outs for PCIe 7.0 and HBM4 on N2P process nodes. This expanded IP portfolio is designed to provide the bandwidth and scalability necessary for data center and automotive applications.