IBM Unveils 0.7nm Chip Architecture to Extend Moore’s Law

The new design marks a significant departure from traditional layouts. While current leading-edge chips rely on nanosheet technology, IBM’s nanostack approach vertically staggers transistors, allowing for distinct material combinations within each layer. This configuration provides a 50 percent boost in performance or a 70 percent increase in energy efficiency compared to the company’s 2 nm chips released in 2021. Researchers presented these findings at the 2026 VLSI symposium, where they also demonstrated a 40 percent scaling improvement in SRAM, a critical factor for managing the massive data demands of generative AI.

Scaling at the Atomic Level

This breakthrough shifts the industry into the angstrom era, where feature dimensions approach the size of individual atoms. Beyond the design itself, IBM is preparing for production by integrating High Numerical Aperture Extreme Ultraviolet (High NA EUV) lithography tools at its Albany, New York facility. Collaborating with partners such as Lam Research and Tokyo Electron, the company aims to move this technology from experimental validation to commercial manufacturing within the next five years. This roadmap suggests at least a decade of continued semiconductor advancement, challenging the long-standing narrative that silicon scaling is nearing a permanent plateau.